1. Field of the Invention
The present invention relates in general to a method of identifying ADIP information, and more particularly, to a method of identifying ADIP information by counting identical bits having the same logic level and counting different bits having different logic levels.
2. Description of the Prior Art
Over the past few years, storage media have rapidly increased in storage capacity due to demand for storing a tremendous amount of information. Of all the various kinds of storage media, optical discs have features of a low-cost, small-size, low-error-rate, long-storage-time, and high-density storage medium and are the most promising dominant storage medium in the future. Generally speaking, optical disc drives are used to read information stored on an optical disc. Examples of optical disc drives are known as compact disc drives (CD-ROM drives) and digital versatile disc drives (DVD-ROM drives) in the prior art. Some optical disc drives have the additional capability of being able to write data onto an optical disc, i.e., CD-R/RW, DVD+R/RW and DVD-R/RW drivers. Optical disc drives are used in music and video playback and are implemented in recording devices and other electronic devices.
In order to effectively manage the information stored on a digital versatile disc, the data storage region of the digital versatile disc is divided into many frames. Data can be stored in these frames according to a memory format. Therefore, while in a writing process for a rewritable digital versatile disc, the DVD drive has to identify the memory format of the rewritable digital versatile disc before the writing process. In order to record the related information concerning the memory frames, there are special addressing structures on the rewritable digital versatile disc to record the related information. According to the specifications of a recordable or a rewritable digital versatile disc, the related information recorded in the addressing structures is known as the address in pre-groove (ADIP).
It is well-known that the information of the ADIP is recorded in the wobble signal by a phase modulation technique, which means that the information is recorded according to the phase shift of a carrier. Every pair of record areas on an optical disc corresponds to 93 wobble cycles, and 8 wobble cycles of them are utilized to record an ADIP by phase modulation. Therefore, an ADIP decoder is required to extract the ADIP from the wobble signal.
Please refer to FIG. 1. FIG. 1 shows a functional block diagram of a prior art optical disc drive system 10. The optical disc drive 10 comprises an optical disc 14 and an optical disc drive 12. The optical disc drive 12 is utilized to write or read a plurality of data to or from the optical disc 14. The optical disc drive 12 comprises an optical pickup 16, a wobble clock generator 18, an ADIP decoder 20, and a controller 22. In addition, the wobble clock generator 18 comprises a phase-locked loop (PLL) 28 and a frequency divider 29, and the ADIP decoder 20 comprises an XOR operation circuit 24 and a decision logic circuit 26.
As is well known in the specifications of a DVD+R disc drive or a DVD+RW disc drive, on the reflecting surface of the optical disc 14, there is a fine spiral track 15. The fine track 15 is composed of two types of tracks, one being a data track to record data having a value of 0 or 1, and the other being a wobble track to record related addressing information. The data track has an interrupt and discontinuity record mark, and the wobble track has an oscillating shape. The surface of the wobble track protrudes beyond the reflecting surface of the optical disc 14. The data track is located inside a groove formed by the raised wobble track. The length of each record mark varies, and the reflection characteristic of the record mark is different from that of the other reflecting surface of the optical disc. Consequently, the ADIP is recorded in the wobble track to assist the process of reading or writing data on the data track by the optical pickup 16. Thereby, the optical pickup 16 is able to extract the tracking information carried by the wobble track of the optical disc 14 and generates a wobble signal WBL. The information of the ADIP is then extracted from the wobble signal WBL by the ADIP decoder 20.
When an access process is being performed on the optical disc 14 by the optical disc drive 12, the optical pickup 16 emits an incident laser beam Li onto the reflecting surface of the optical disc 14, and the reflecting surface of the optical disc 14 reflects a corresponding reflected laser beam Lr back to the optical pickup 16. The intensity of the reflected laser beam Lr is then detected by a plurality of optical sensors (not shown) of the optical pickup 16 and is transformed to a plurality of electrical signals. By performing some well-known subtracting processes over the plurality of electrical signals, the wobble signal WBL can be generated. The wobble signal WBL is then forwarded to both the wobble clock generator 18 and the ADIP decoder 20. Thereafter, a non-phase-modulated wobble clock WBLCLK is generated by the wobble clock generator 18 based on the phase-modulated wobble signal WBL. As is shown in FIG. 1, the wobble signal WBL is first processed by the phase-locked loop 28 to generate a non-phase-modulated clock signal WOBCLK having a high frequency, the high-frequency clock signal WOBCLK is then processed by the frequency divider 29 to generate the wobble clock WBLCLK. In addition, the high-frequency clock signal WOBCLK is also utilized to generate other clock signals having different frequencies for driving other devices with the frequency divider 29. For instance, the frequency divider 29 generates a clock signal WBLCLK2 having a frequency that is twice the frequency of the wobble clock WBLCLK.
The XOR operation circuit 24 performs an XOR operation over the wobble clock WBLCLK and the wobble signal WBL and generates a calculation result ADIP_PRE. Subsequently, the decision logic circuit 26 is able to determine whether an effective ADIP is included in the calculation result ADIP_PRE. If there is an effective ADIP included in the calculation result ADIP_PRE, the ADIP is then forwarded to the controller 22. Thereafter, the controller 22 is able to access the data of the optical disc 14 with the aid of the ADIP.
FIGS. 2–4 are diagrams of schematic waveforms of the prior art wobble signals 30a, 30b, and 30c, having a time scale along the abscissa. The wobble signal 30a shown in FIG. 2 comprises 8 wobble cycles W0, W1, W2, W3, W4, W5, W6, and W7, which are utilized to record the information of an ADIP by phase modulation. As is shown in FIG. 2, a phase shift of 180° occurs at the beginning of the first phase-modulated cycle W0 of the wobble signal 30a. In addition, a phase shift of 180° also occurs between the wobble cycle W3 and the wobble cycle W4 of the wobble signal 30a. Consequently, the wobble signal 30a corresponds to an ADIP sync unit. As aforementioned, the wobble clock generator 18 is able to generate wobble clock WBLCLK based on the wobble signal 30a which is a phase-modulated signal. As is shown in FIG. 2, the wobble clock WBLCLK is a non-phase-modulated signal. Consequently, the ADIP recorded in the phase-modulated wobble signal 30a can be extracted by an XOR operation of the XOR operation circuit 24 with the aid of the wobble clock WBLCLK. Based on a cycle of the wobble clock WBLCLK as a unit, the cycle of the wobble signal 30a which is in phase with the cycle of the wobble clock WBLCLK corresponds to a bit of 1, and the cycle of the wobble signal 30a which is in opposite phase with the cycle of the wobble clock WBLCLK corresponds to a bit of 0. Accordingly, the ADIP sync unit of the wobble signal 30a corresponds to a bit stream of “11110000”.
The wobble signal 30b shown in FIG. 3 comprises 8 wobble cycles W0, W1, W2, W3, W4, W5, W6, and W7, which are utilized to record the information of an ADIP by phase modulation. As is shown in FIG. 3, a phase shift of 180° occurs at the beginning of the first phase-modulated cycle W0 of the wobble signal 30b. In addition, a phase shift of 180° also occurs between the wobble cycle W0 and the wobble cycle W1 of the wobble signal 30b, and a phase shift of 180° further occurs between the wobble cycle W5 and the wobble cycle W6 of the wobble signal 30b. Consequently, the wobble signal 30b corresponds to an ADIP data unit having a corresponding logic level of 0. Similarly, the wobble clock generator 18 is able to generate wobble clock WBLCLK based on the wobble signal 30b which is a phase-modulated signal. As is shown in FIG. 3, the wobble clock WBLCLK is a non-phase-modulated signal. Consequently, the ADIP recorded in the phase-modulated wobble signal 30b can be extracted by an XOR operation of the XOR operation circuit 24 with the aid of the wobble clock WBLCLK. Based on a cycle of the wobble clock WBLCLK as a unit, the cycle of the wobble signal 30b which is in phase with the cycle of the wobble clock WBLCLK corresponds to a bit of 1, and the cycle of the wobble signal 30b which is in opposite phase with the cycle of the wobble clock WBLCLK corresponds to a bit of 0. Accordingly, the ADIP data unit of the wobble signal 30b having a logic level of 0 corresponds to a bit stream of “10000011”.
The wobble signal 30c shown in FIG. 4 comprises 8 wobble cycles W0, W1, W2, W3, W4, W5, W6, and W7, which are utilized to record the information of an ADIP by phase modulation. As is shown in FIG. 4, a phase shift of 180° occurs at the beginning of the first phase-modulated cycle W0 of the wobble signal 30c. In addition, a phase shift of 180° also occurs between the wobble cycle W0 and the wobble cycle W1 of the wobble signal 30c, and a phase shift of 180° further occurs between the wobble cycle W3 and the wobble cycle W4 of the wobble signal 30c. Consequently, the wobble signal 30c corresponds to an ADIP data unit having a corresponding logic level of 1. Similarly, the wobble clock generator 18 is able to generate the wobble clock WBLCLK based on the wobble signal 30c which is a phase-modulated signal. As is shown in FIG. 4, the wobble clock WBLCLK is a non-phase-modulated signal. Consequently, the ADIP recorded in the phase-modulated wobble signal 30c can be extracted by an XOR operation of the XOR operation circuit 24 with the aid of the wobble clock WBLCLK. Based on a cycle of the wobble clock WBLCLK as a unit, the cycle of the wobble signal 30c which is in phase with the cycle of the wobble clock WBLCLK corresponds to a bit of 1, and the cycle of the wobble signal 30c which is in opposite phase with the cycle of the wobble clock WBLCLK corresponds to a bit of 0. Accordingly, the ADIP data unit of the wobble signal 30c having a logic level of 1 corresponds to a bit stream of “10001100”.
According to the well-known specifications of the DVD+R optical drive and the DVD+RW optical drive, an ADIP unit corresponds to 93 wobble cycles and 8 wobble cycles of them are utilized to record an ADIP sync unit or an ADIP data unit by phase modulation. Accordingly, when the XOR operation circuit 24 performs XOR operations over the wobble signal WBL and the wobble clock WBLCLK to generate the calculation result ADIP_PRE, a bit stream of “11110000” of the calculation result ADIP_PRE will correspond to the ADIP sync unit of the wobble signal WBL. A comparison between the calculation result ADIP_PRE and the bit stream of “11110000” performed by the decision logic circuit 26 is able to determine whether the current wobble signal WBL corresponds to an ADIP sync unit.
Similarly, when the XOR operation circuit 24 performs XOR operations over the wobble signal WBL and the wobble clock WBLCLK to generate the calculation result ADIP_PRE, a bit stream of “10000011” of the calculation result ADIP_PRE will correspond to the ADIP data unit of the wobble signal WBL having a logic level of 0. A comparison between the calculation result ADIP_PRE and the bit stream of “11110000” performed by the decision logic circuit 26 is able to determine whether the current wobble signal WBL corresponds to an ADIP data unit having a logic level of 0. Likewise, when the XOR operation circuit 24 performs XOR operations over the wobble signal WBL and the wobble clock WBLCLK to generate the calculation result ADIP_PRE, a bit stream of “10001100” of the calculation result ADIP_PRE will correspond to the ADIP data unit of the wobble signal WBL having a logic level of 1. A comparison between the calculation result ADIP_PRE and the bit stream of “11110000” performed by the decision logic circuit 26 is able to determine whether the current wobble signal WBL corresponds to an ADIP data unit having a logic level of 1.
The schematic waveforms of the prior art wobble signals 30a, 30b, and 30c shown in FIGS. 2–4 are actually ideal waveforms for recording the ADIP data units and the ADIP sync units. However, the wobble signal WBL generated by the optical pickup 16 is affected by various kinds of factors. For instance, owing to the variation of the rotating speed of the spindle motor of the disc drive or any vibration caused by the disc eccentricity and the unstable light power of the emitting laser beam by the optical pickup 16, the variation of the light power of the reflected laser beam Lr may occur. In other words, because of the abovementioned interferences, the real waveforms of the wobble signals 30a, 30b, and 30c normally deviate from the ideal waveforms. Consequently, according to the prior art optical disc drive 12, the decision logic circuit 26 is required to perform a plurality of comparing operations to determine whether an effective ADIP is included in the calculation result ADIP_PRE. For instance, when the decision logic circuit 26 identifies a calculation result ADIP_PRE to be a bit stream of “10000111”, although the bit stream of “10000111” is different from the bit stream of “10000011”, the decision logic circuit 26 will still identify the calculation result ADIP_PRE to be an ADIP data unit having a logic level of 0, which actually corresponds to a bit stream of “10000011”. In other words, the abovementioned interferences over the wobble signal WBL have been taken into consideration by the operation of the decision logic circuit 26. Therefore, when the decision logic circuit 26 determines whether an effective ADIP is included in the calculation result ADIP_PRE, the decision logic circuit 26 is required to utilize a plurality of predetermined bit streams for a sequential comparing process to identify the calculation result ADIP_PRE. Consequently, a plurality of the registers are required by the decision logic circuit 26 to record the plurality of the predetermined bit streams and to perform a complex comparing operation, which causes a complicated and high-cost circuit for the optical disc drive 12.